The present invention relates generally to the data processing field, and more particularly, relates to a method and a phase redundant regulator apparatus for implementing redundancy at a phase level.
As the demand for reliability of electronic equipment and other hardware increases, the use of redundancy in regulator designs advantageously may be implemented. Various regulator arrangements are known in the art.
For example, FIG. 1 illustrates a known regulator design, a conventional buck regulator topology. The conventional buck regulator typically includes a pair of field effect transistors (FETs) Q1, Q2, a control module M1, an input capacitor C1, an output capacitor C2, and an inductor L1 coupled in series between FET Q1 and the output voltage Vout. An input voltage Vin is converted to an output voltage Vout by controlling the on time of FET Q1 and the off time FET Q2 using the control module M1 that receives the output voltage Vout feedback and provides a control or gate input to each of the FETs Q1, Q2.
FIG. 2 illustrates a typical multi-phase buck regulator arrangement. As output currents have increased, multi-phase controllers have been increasingly used. The illustrated multi-phase buck regulator basically includes three buck converters that would be controlled by having their gate drive signals generated 120 degrees apart. The three buck converters are controlled out of phase from each other by the common control module M1. Controlling the three buck converters out of phase generally improves both input and output ripple current, ripple and response time.
FIG. 3A shows a prior art multi-phase buck regulator arrangement with the buck regulators connected in parallel. It is also common that the buck or other regulator and multi-phase regulators may be connected in parallel. This parallel arrangement has been provided to increase the available output current, but not for redundant operation. The prior art multi-phase buck regulator arrangement is not effective as a redundant configuration for the following reasons. First, shorts of the off-time FET Q2 or output capacitor C2 will bring down the output. Second, shorts of the on-time FET Q1 results in over voltage of the output voltage and an over current of the input voltage source. Third, shorts of the input capacitor C1 will also cause an over current of the input voltage source. FIGS. 4-6 illustrate conventional arrangements to handle the above listed problems at a regulator level. Fourth, an average current share method typically is provided for a multiple regulator system, such as the illustrated multi-phase buck regulator arrangement of FIG. 3A. However, the average current share method does not work for redundant regulator systems. With an average current share method, each regulator phase is to run at the load current divided by the number of regulator phases, but when one fails the average includes the failed unit so current sharing between the remaining ones fails.
Referring also to FIG. 3B, each of the multi-phase controllers M1 of FIG. 3A generates control signals to sequentially activate each of the plurality of regulator phases 1-3 for predetermined periods of time to generate controlled current sharing output current pulses on a periodic basis. Multi-phase controller M1 provides respective gate drive signals applied to each of the multi-phases FETs. Gate drive Q1A is applied to FET Q1A, gate drive Q2A is applied to FET Q2A; gate drive Q1B is applied to FET Q1B, gate drive Q2B is applied to FET Q2B; gate drive Q1C is applied to FET Q1C, and gate drive Q2C is applied to FET Q2C. As shown this is a three-phase design where the gate drives between phases are 120 degrees out of phase. Also the inductor currents of each of the phases are shown as, IL1A, IL1B, and IL1C, where each phase supplies one third of the load current and has AC current component that is 120 degrees out of phase from the other phases.
FIG. 4 shows a respective ORing device or diode D1, D2 with the illustrated two regulators to prevent the output voltage going down due to a short of the off-time FET Q2 or output capacitor C2. Alternatively, a FET is often used instead of a diode. When an ORing FET is used negative current detection/protection is required to make the FET work like a true diode and only allows current to flow out of the regulator and not into the regulator.
FIG. 5 shows a traditional circuit for protection of shorts of the on-time FET Q1 from causing over voltage (OV) of the output voltage. This is done by sensing the output voltage and firing an SCR, X1, to short the input and blow an input fuse F1. This arrangement works to protect the output load, but fuses are generally slow and will most likely cause the system to shut down due to an over current fault on the power supply that supplies the input voltage.
FIG. 6 shows a prior art circuit that has been used for over voltage protection to replace the fuse circuit of FIG. 5 that works at greater speed. In FIG. 6, the fuse F1 is replaced by a third FET Q3 with a latch activated by an over voltage detect that provides a control or gate input to turn off FET Q3 and open the input voltage Vin.
FIG. 7 illustrates a conventional arrangement of multiple regulators, REG 1, REG 2, and REG 3 in a N+1 redundant fashion, where N is the number of regulators required to satisfy a required system capacity and one extra regulator is provided for redundant operation. Initially each of the three regulators REG 1, REG 2, and REG 3 operate at ⅔ capacity. When one of the three regulators fails, such as REG 1, then the remaining regulators, REG 2, and REG 3 operate at full capacity to satisfy the required system capacity. For example, with a system capacity of 200 amps, three regulators each having 100 amp capacity are used.
The problem of current sharing in redundant systems is addressed by using another current share method rather than the average current share. Other known current sharing methods include a master-slave current share method, where the regulator that supplies the highest current controls the bus and other regulators are adjusted upwardly. An impedance current share has been used where tight regulation is required and current share is based on system impedance. Also a common error voltage has been used for current mode controlled regulators.
As shown in FIG. 7, ORing devices, D1, D2, and D3 are used on the respective regulator outputs, and a master/slave current share method is used with a fuse or FET protection method used for over voltage protection. It should be noted that a FET protection circuit, though known, has not been used for redundant operation, but as replacement for the slower fuse method. Other redundant designs may use isolated topologies where shorts of the FETs cannot cause over voltage and these circuits are not required.
A need exists for an improved mechanism for implementing redundancy in regulator designs.
A principal object of the present invention is to provide a method and a phase redundant regulator apparatus for implementing redundancy in regulator designs. Other important objects of the present invention are to provide such method for implementing redundancy in regulator designs and phase redundant regulator apparatus substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and a phase redundant regulator apparatus are provided for implementing redundancy in regulator designs. A plurality of regulator phases are connected in parallel between a regulator input and a regulator output, each of the plurality of regulator phases including a regulator receiving an input voltage and providing an output voltage. A multi-phase controller is coupled to each of the plurality of regulator phases. The multi-phase controller receives a feedback output voltage and a respective detected current signal from each of the plurality of regulator phases. The multi-phase controller generates control signals to sequentially activate each of the plurality of regulator phases for predetermined periods of time to generate controlled current sharing between phases. Each of the plurality of regulator phases includes an output ORing device to limit reverse current flow into each of the phase outputs, an input protection device for providing input over current protection and output over voltage protection of each phase, and a current sharing method for maintaining current sharing between all active phases after a failure of one or more regulator phases with one or more regulator phases provided for enabling redundancy.